A passive CMOS low-pass filter for high speed and high SNDR applications

A new passive switched-capacitor low-pass filter topology is presented. The sampling rate is high due to the reduced number of clock phases and switches connected to each capacitor. Also, this scheme decreases the filter nonlinearity. Verified by simulations, the noise analysis of the filter shows superior performance compared to active SC filters. These features, and a wide frequency tuning range, make the filter suitable for high-speed, low noise, and low power applications. A 7^th-order 400 MS/s filter was designed in 0.18 μm AKM CMOS technology. Simulations verify that it can achieve over 100 dB attenuation at 200 MHz frequency, while consuming only dynamic power.