A 0.5-V 1.28-MS/s 10-bit SAR ADC with switching detect logic

This paper presents a 10-bit successive approximation register (SAR) ADC with a detect logic for DAC switching. The proposed switching detect logic can avoid switch power wasted and reduce the impact of capacitor mismatch from the layout parasitic as well as improve the resolution performance of SAR ADC. The ADC consumes 3 uW at 0.5-V supply and 1.28-MS/s sampling rate, achieves high ENOB and FOM performance of 9.95-bit and 2.36 fJ/conversion-step, respectively. This SAR ADC is fabricated with the TSMC 90 nm CMOS process and occupies an active area of 238μm×200μm.