Quadrature-Phase Topology of a High Frequency Ring Oscillator

Phase-locked loops (PLLs) are used to implement a variety of timing related functions such as frequency synthesis, clock and data recovery, and clock de-skewing. Any jitter or phase noise in the output of the PLL used in these applications generally degrades the performance margins of the system in which it resides and so is of great concern to the designers of such systems. Jitter and phase noise are different ways of referring to an undesired variation in the timing of events at the output of the PLL. In this paper an improved Voltage Controlled Oscillator (VCO) design is introduced using quadrature phase signals. It has been implemented on 0.35 mum CMOS technology, so the complete layout has been designed as well. The operation is presented with simulation results. The carrier frequency is around 2.4 GHz during transmission according to the ZigBee standard.