Prototyping Generators for on-line test vector generation based on PSL properties

From an assumed property, which constrains the inputs of a design under test, we produce a RTL synthesizable design that generates compliant sequences of values for all the signals named in the property. Such generator can be connected to the design under test for verification by simulation or emulation. Experiments on our prototype tool show that the technique is efficient, and allows to test the design at its full speed when implemented on an FPGA platform.