A compact AES encryption core on Xilinx FPGA

Author

Kundi, Dur-e-Shahwar ; Zaka, Saleha ; Qurat-Ul-Ain ; Aziz, Arshad

Author_Institution

PN Eng. Coll., Nat. Univ. of Sci. & Technol., Karachi

fYear

2009

fDate

17-18 Feb. 2009

Firstpage

1

Lastpage

4

Abstract

This paper presents an Advanced Encryption Standard (AES) encryption core on Field Programmable Gate Array (FPGA). The target device is Spartan-3 FPGA. We have designed an efficient and compact, iterative architecture with input and key, both of 128 bits. The throughput achieved is 2640.3712 Mbps with a frequency of 206.28 MHz; using 8 embedded Block RAMs (BRAMs) and 390 Slices. The aim is to provide a fast encryption core for small size and low cost applications.

Keywords

cryptography; field programmable gate arrays; iterative methods; logic design; random-access storage; AES encryption core; Spartan-3 FPGA; Xilinx FPGA; advanced encryption standard encryption core; bit rate 2640.3712 Mbit/s; embedded block RAMs; field programmable gate array; frequency 206.28 MHz; iterative architecture; Communication networks; Costs; Cryptography; Data privacy; Educational institutions; Field programmable gate arrays; Frequency; NIST; Testing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer, Control and Communication, 2009. IC4 2009. 2nd International Conference on

Conference_Location

Karachi

Print_ISBN

978-1-4244-3313-1

Electronic_ISBN

978-1-4244-3314-8

Type

conf

DOI

10.1109/IC4.2009.4909251

Filename

4909251