Low-resistance CVD W plug on Ti silicide for advance CMOS applications

Author

Young, K.K. ; Bradbury, D.R. ; Uesato, W. ; Hu, H.K. ; Kruger, J.B. ; Chiu, K.Y.

Author_Institution

Hewlett Packard Co., Palo Alto, CA, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

928

Lastpage

930

Abstract

A novel approach is used to form a selective CVD (chemical-vapor-deposited) W plug on a Ti silicide surface by adding a nucleation layer in the contact hole. The technique is called SANIC (self-aligned nucleation layer formation in the contact). The process sequences of SANIC are described and the process latitude of the SANIC technique is examined. The SANIC process has been demonstrated on 1- mu m (drawn) CMOS SRAM and ring oscillators. The CMOS device characteristics and the corresponding gate delays of ring oscillators are shown.<>

Keywords

CMOS integrated circuits; CVD coatings; chemical vapour deposition; integrated circuit technology; metallisation; tungsten; 1 micron; SANIC; SRAM; W plug; W-TiSi/sub 2/; advance CMOS applications; chemical-vapor-deposited; contact hole; device characteristics; gate delays; low resistance CVD; ring oscillators; selective CVD; self-aligned nucleation layer formation; CMOS process; Chemical vapor deposition; Delay; Plugs; Random access memory; Ring oscillators; Silicides;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237011

Filename

237011