Title :
A low-power dual-clock strategy for digital circuits of EPC Gen2 RFID tag
Author :
Luo, Qiasi ; Guo, Li ; Li, Qing ; Zhang, Gang ; Wang, Junyu
Author_Institution :
Dept. of Electron. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei
Abstract :
Power consumption is critical to the performance of EPC Gen2 RFID tags. System clock frequency of tags should be as low as possible to reduce the power consumption and still conform to the protocol. This paper analyses the impact of different clock strategies on digital circuits of EPC Gen2 tag. An error shift approach is proposed to reduce the backscatter link frequency (BLF) errors. A dual-clock strategy with both 1.28 and 2.56 MHz clocks for the digital circuits is developed. Compared with the 1.92 MHz unitary-clock strategy, the dual-clock strategy offers larger decoding margins and BLF margins, consumes 5.66% to 9.44% less power estimated in CMOS 0.18 mum technologies, and fully conforms to the EPC Gen2 protocol as well.
Keywords :
CMOS digital integrated circuits; UHF integrated circuits; decoding; low-power electronics; protocols; radiofrequency identification; CMOS technologies; EPC Gen2 RFID tag; backscatter link frequency errors; decoding margins; digital circuits; error shift approach; frequency 1.28 MHz; frequency 1.92 MHz; frequency 2.56 MHz; low-power dual-clock strategy; power consumption; protocol; size 0.18 mum; system clock frequency; Backscatter; Clocks; Decoding; Digital circuits; Encoding; Energy consumption; Frequency; Protocols; RFID tags; Radiofrequency identification; EPC Gen2; RFID; backscatter frequency; clock strategy; protocol conformance;
Conference_Titel :
RFID, 2009 IEEE International Conference on
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4244-3337-7
Electronic_ISBN :
978-1-4244-3338-4
DOI :
10.1109/RFID.2009.4911177
