A scan design method based on two complementary connection styles to minimize test power

Scan design is a good design-for-testability (DfT) discipline but always incurs high power dissipation during test application. Scan cell ordering is a simple yet effective scan path organization method to reduce the test power. In this paper, we propose a new scan chain ordering method based on two complementary scan cell connection styles. To minimize the transitions during the shifting of test data, we evaluate the connection cost between two scan cells based on the exact number of transitions caused by them during test instead of the Hamming distance between their test data. The test power can be minimized as it is proportional to the number of overall transitions. We applied our method on several benchmark circuits. The experimental results show that the scan designs by our method can always achieve the lower test power than those by other existing scan cell ordering methods.