Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT

Author

Yamada, S. ; Yokoyama, S. ; Koyanagi, M.

Author_Institution

Res. Center for Integrated Syst., Hiroshima Univ., Japan

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

859

Lastpage

862

Abstract

A novel two-dimensional device simulator for poly-Si TFTs (thin-film transistors) is developed, in which the effects of grain boundaries (GBs) are incorporated into the carrier mobility model. In this simulator, the basic semiconductor equations are iteratively solved in combination with the carrier generation/recombination model, which consists of avalanche, S-R-H, and Auger processes. By using this simulator, the effects of GBs on device characteristics are accurately evaluated. In addition, the avalanche-induced short channel effect in poly-Si TFTs is numerically analyzed.<>

Keywords

carrier mobility; electron-hole recombination; elemental semiconductors; grain boundaries; impact ionisation; semiconductor device models; silicon; thin film transistors; Auger processes; Schottky Read Hall recombination; Si; avalanche induced short channel effect; carrier generation/recombination model; carrier mobility model; grain boundaries (GBs); numerical analysis; polysilicon TFT; thin-film transistors; two-dimensional device simulator; Equations; Grain boundaries; Radiative recombination; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237027

Filename

237027