New architecture for high data rate turbo decoding of product codes

This paper presents a new circuit architecture for turbo decoding, which achieves very high data rates when using product codes as error correcting codes. Although this architecture is independent of the elementary code (convolutional or block) used and of the corresponding decoding algorithms, we focus here on the case of product codes. This innovative circuit architecture stores several data at the same address and performs parallel decoding to increase the data rate. It is able to process several data simultaneously with one memory (classical designs require m memories); its latency decreases when the amount of data processed simultaneously is large. We present results on block turbo decoder designs of 2-data, 4-data and 8-data decoders (where 2, 4 and 8 are the number of data symbols processed simultaneously). For each decoder circuit, the latency is decreased, the area of the processing unit is increased by a factor m and the critical path and memory size are constant (the data rate is increased by m² if we have m parallel decoders).