HSST BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverter

HSST/BiCMOS technology has been developed by merging a novel 0.3 mu m self-aligned double-poly bipolar process called high-performance super self-aligned process technology (HSST) and the 0.22 mu m CMOS process. The HSST bipolar transistor size is 2.5 times smaller than that of 1 mu m SST-1B with an emitter 0.4 mu m wide. This results from a 0.3 mu m design rule, a collector polysilicon trench electrode, and oxide-filled trench isolation. Owing to the horizontal shrinking and high cutoff frequency of 22.3 GHz at V/sub ce/=1 V, the ECL (emitter coupled logic) gate attains 25.4 ps/G at 1.58 mA. For the 0.2 mu m CMOS inverter, gate delays of 44.5 ps/G at V/sub dd/=2 V and 32.8 ps/G at 3 V are obtained. The BiCMOS gate also operates up to 116 ps/G at 2 V, 66.1 ps/G at 3 V, and 52.1 ps/G at 4 V.<>