Title :
A 5.9 mu m/sup 2/ super low power SRAM cell using a new phase-shift lithography
Author :
Yamanaka, T. ; Hasegawa, N. ; Tanaka, T. ; Ishibashi, K. ; Hashimoto, T. ; Shimizu, A. ; Hashimoto, N. ; Sasaki, K. ; Nishida, T. ; Takeda, E.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A novel 5.89 mu m/sup 2/ memory cell for 16 Mb SRAMs has been developed. The cell is fabricated using a phase-shift photolithography that includes a method for making 0.25 mu m space patterns with the conventional stepper. To reduce cell area, the concept of small cell-ratio is introduced. To overcome the unstable operation of the small-ratio cell, an advanced poly-Si PMOS transistor for load devices is used. To simultaneously obtain stable operation and extremely low standby power dissipation for the memory cell, a self-aligned offset structure for the poly-Si PMOS transistor is proposed and demonstrated. An extremely small leakage current of 2-fA/cell and an on/off-current ratio of 4.6*10/sup 6/ are achieved with this transistor in a memory cell. Memory operation is also demonstrated by an experimental 32 kb SRAM chip.<>
Keywords :
MOS integrated circuits; SRAM chips; integrated circuit technology; photolithography; 0.25 micron; 16 Mbit; 32 kbit; SRAM cell; advanced poly-Si PMOS transistor; leakage current; load devices; low standby power dissipation; memory cell; phase-shift lithography; photolithography; polycrystalline Si; polysilicon devices; self-aligned offset structure; small cell-ratio; stable operation; static RAM; super low power; Leakage current; Lithography; MOSFETs; Power dissipation; SRAM chips;
Conference_Titel :
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1990.237064
