• DocumentCode
    3316869
  • Title

    Comparison of low-power biopotential processors for on-the-fly spike detection

  • Author

    Gagnon-Turcotte, G. ; Camaro, C.-O Dufresne ; Gosselin, B.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. Laval, Quebec City, QC, Canada
  • fYear
    2015
  • fDate
    24-27 May 2015
  • Firstpage
    802
  • Lastpage
    805
  • Abstract
    Spike detection is a signal processing technique that can enable significant data rate reduction and resource savings in wireless brain monitoring. In these systems, energy-efficient spike detection algorithms are sought for enabling realtime signal processing while consuming low-power. As several spike detectors are based on ASIC, FPGA or low-power microcontroller unit (MCU), such algorithms must add little overhead to the entire system, while ensuring low error rate. In this paper, we present a comparative study of three different spike detection algorithms targeted toward implementation into low-power resource-constrained electronic systems. As practical validation, all candidate algorithms have been implemented on a popular low-power MCU and were fully characterized experimentally using previously recorded neural signals with different signal-to-noise ratios. A cost function based on detection rates, execution times, power consumption and resource utilization have been created and employed for comparing the detectors. The performances of all candidates are reported, and the best detector is identified. All candidate detectors present detection rate above 95% at high SNR, and above 78% for low SNR and can reduce the power consumption by up to 22.7%. This paper is the first to demonstrate the performances and hardware limitations of spike detectors on a low-power MCU system.
  • Keywords
    application specific integrated circuits; bioelectric potentials; biomedical electronics; brain; field programmable gate arrays; medical signal processing; microcontrollers; neurophysiology; patient monitoring; power consumption; signal denoising; ASIC; FPGA; data rate reduction; energy-efficient spike detection algorithms; low-power MCU; low-power biopotential processors; low-power microcontroller unit; low-power resource-constrained electronic systems; neural signals; on-the-fly spike detection; power consumption; resource savings; resource utilization; signal processing technique; signal-to-noise ratios; spike detectors; wireless brain monitoring; Cost function; Detectors; Power demand; Resource management; Signal to noise ratio; Transceivers; Wireless communication; Spike detection; brain-computer interfaces; energy-efficent biosignal processing; neural recording;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
  • Conference_Location
    Lisbon
  • Type

    conf

  • DOI
    10.1109/ISCAS.2015.7168755
  • Filename
    7168755