Savage16 - 16-bit RISC architecture general purpose microprocessor

Author

Gheorghe, Andrei-Sorin ; Burileanu, Corneliu

Author_Institution

Univ. Politeh. of Bucharest, Bucharest, Romania

Volume

02

fYear

2010

fDate

11-13 Oct. 2010

Firstpage

521

Lastpage

524

Abstract

This paper describes the architecture and the internal structure of “Savage16”, a fully functional general purpose reduced instruction set microprocessor, with a modified Harvard, five stage pipeline architecture. The memory organization and key architecture elements are being described, as well as the hardware block diagram and the internal structure. A summary of the instruction set is presented, along with a brief description of the addressing modes.

Keywords

interrupts; memory architecture; microprocessor chips; pipeline processing; reduced instruction set computing; storage allocation; RISC architecture; SAVAGE16; addressing mode; five stage pipeline architecture; general purpose microprocessor; hardware block diagram; internal structure; key architecture; memory organization; reduced instruction set microprocessor; Clocks; Hardware; Microprocessors; Pipelines; Radiation detectors; Random access memory; Registers; RISC; instruction set; interrupts; memory organization; pipeline;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference (CAS), 2010 International

Conference_Location

Sinaia

ISSN

1545-827X

Print_ISBN

978-1-4244-5783-0

Type

conf

DOI

10.1109/SMICND.2010.5650480

Filename

5650480