Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU

Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process.