DocumentCode :
3317041
Title :
A real-time architecture for reference frame compression for high definition video coders
Author :
Silveira, Dieison ; Povala, Guilherme ; Amaral, Livia ; Zatt, Bruno ; Agostini, Luciano ; Porto, Marcelo
Author_Institution :
Group of Archit. & Integrated Circuits, Fed. Univ. of Pelotas - Pelotas, Pelotas, Brazil
fYear :
2015
fDate :
24-27 May 2015
Firstpage :
842
Lastpage :
845
Abstract :
Current battery-powered devices that manipulate digital videos must consider the energy consumption of this process as an important issue, especially when high or ultra-high definition videos are handled. In this scenario, this paper proposes a solution to reduce the energy consumption in video coding systems by reducing the external memory communication during the motion estimation. The scheme presented in this paper is called Differential Reference Frame Coder and it implements an algorithm that combines two techniques to reduce the memory bandwidth: a differential coding based on a simplified intra-prediction process, to reduce the spatial redundancy of the reconstructed samples, and a semi-fixed length coding applied in the residues generated by the differential coding step. This solution reaches an average lossless compression ratio higher than 57% for the evaluated HD 1080p video sequences whereas supporting random access to reference frame blocks. The proposed hardware architectures (Coder and Decoder) were described in VHDL and synthesized targeting ASIC for 65nm and 180nm TSMC standard-cell libraries. The results show that with 65nm, the architectures are able to process UHD 2160p (3840×2160 samples) at 30 fps or HD 1080p (1920×1080 samples) at 120 fps with a power dissipation of 0.885mW.
Keywords :
application specific integrated circuits; data compression; energy consumption; hardware description languages; high definition video; integrated circuit design; motion estimation; telecommunication power management; video codecs; video coding; ASIC; HD video sequences; TSMC standard-cell libraries; VHDL; application specific integrated circuits; battery-powered devices; decoder; differential coding; differential reference frame coder; digital videos; energy consumption; external memory communication; high definition video coders; intraprediction process; lossless compression ratio; memory bandwidth; motion estimation; power dissipation; reference frame compression; semifixed length coding; spatial redundancy; ultra-high definition videos; video coding systems; Decoding; Encoding; Hardware; High definition video; Memory management; Power dissipation; Video coding; VLSI architectures; memory bandwidth reduction; reference frame compression; video coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
Type :
conf
DOI :
10.1109/ISCAS.2015.7168765
Filename :
7168765
Link To Document :
بازگشت