DocumentCode
3317070
Title
Delay calibration circuit for delay lines
Author
Pandita, Bupesh
fYear
2015
fDate
24-27 May 2015
Firstpage
850
Lastpage
853
Abstract
A circuit for delay calibration of delay lines has been proposed. The proposed circuit is attractive for forwarded-clock links. Novel delay cell and a clock conditioning block reduce startup and false lock problems. The proposed wide-range calibration circuit has been realized in a 28nm CMOS process.
Keywords
CMOS integrated circuits; calibration; delay lines; CMOS process; clock conditioning block; delay calibration circuit; delay cell; delay lines; forwarded clock link; size 28 nm; Calibration; Clocks; Computer architecture; Delay lines; Delays; Phase frequency detector; Receivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location
Lisbon
Type
conf
DOI
10.1109/ISCAS.2015.7168767
Filename
7168767
Link To Document