Electrical characterization of textured interpoly capacitors for advanced stacked DRAMs

Author

Fazan, P.C. ; Ditali, A.

Author_Institution

Micron Technol. Inc., Boise, ID, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

663

Lastpage

666

Abstract

The authors present and discuss the C-V, I-V and TDDB (time-dependent dielectric breakdown) characteristics of textured interpoly capacitors fabricated with different process conditions. It is concluded that the combination of a rough storage electrode with a dielectric that has a bulk-limited conduction offers a considerable increase in capacitance while improving device reliability. Textured stacked capacitors (TSTCs) are proposed for the manufacture of 64-Mb DRAMs. Compared to other advanced stacked capacitor concepts, the approach drastically reduces process complexity and topography.<>

Keywords

DRAM chips; capacitors; circuit reliability; electric breakdown of solids; 64 Mbit; C-V characteristics; I-V characteristics textured stacked capacitors; TDDB; bulk-limited conduction; device reliability; process complexity; rough storage electrode; stacked DRAMs; textured interpoly capacitors; time-dependent dielectric breakdown; topography; Capacitance; Capacitors; Dielectric breakdown; Dielectric devices; Electrodes; Manufacturing; Surfaces;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237112

Filename

237112