Process integration for 64 M DRAM using an asymmetrical stacked trench capacitor (AST) cell

Author

Sunouchi, K. ; Horiguchi, F. ; Nitayama, A. ; Hieda, K. ; Takato, H. ; Okabe, N. ; Yamada, T. ; Ozaki, T. ; Hashimoto, K. ; Takedai, S. ; Yagishita, A. ; Kumagae, A. ; Takahashi, Y. ; Masuoka, F.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

647

Lastpage

650

Abstract

The key points of sub-half-micron CMOS technologies for 64-Mb DRAM fabrication are described. The main features of the technologies are (1) an asymmetrical stacked trench capacitor (AST) cell, (2) localized channel implantation through the field oxide (LIF), and (3) a 0.4- mu m transistor with LDD (lightly doped drain) n/sup -/ impurity of arsenic. The lithographic levels are 0.4 mu m for critical layers. achieved using a KrF excimer laser stepper. The AST cell has a stacked capacitor in a trench; the trenches are located asymmetrically with respect to each other. A small cell area of 1.53 mu m/sup 2/ has been achieved by adopting the LIF isolation and the As LDD transistor for the AST cell. An experimental 64-Mb DRAM chip has been successfully fabricated using these technologies.<>

Keywords

CMOS integrated circuits; DRAM chips; VLSI; photolithography; 0.4 micron; 64 Mbit; DRAM fabrication; LDD; LIF isolation; asymmetrical stacked trench capacitor; cell area; excimer laser stepper; lithographic levels; localized channel implantation; sub-half-micron CMOS technologies; trenches; CMOS technology; Capacitors; Fabrication; Impurities; Isolation technology; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237116

Filename

237116