DocumentCode :
3317614
Title :
Accelerating compressive sensing reconstruction OMP algorithm with CPU, GPU, FPGA and domain specific many-core
Author :
Kulkarni, Amey ; Mohsenin, Tinoosh
Author_Institution :
Dept. of Comput. Sci. & Electr. Eng., Univ. of Maryland, Baltimore, MD, USA
fYear :
2015
fDate :
24-27 May 2015
Firstpage :
970
Lastpage :
973
Abstract :
Compressive Sensing (CS) signal reconstruction can be implemented using convex relaxation, non-convex, or local optimization algorithms. Though the reconstruction using convex optimization, such as the Iterative Hard Thresholding algorithm, is more accurate than matching pursuit algorithms, most researchers focus on matching pursuit algorithms because they are less computationally complex. Orthogonal Matching Pursuit (OMP) is a greedy algorithm, which solves the problem by choosing the most significant variable to reduce the least square error. In this paper, we propose an efficient parallel architecture for OMP CS reconstruction. For architecture implementation, we perform measurement and sparsity analysis to reduce the complexity. The proposed architecture is platform independent and is implemented on 7 different platforms including general purpose CPUs, GPUs, a Virtex-7 FPGA and a domain specific many-core. The implementation results indicate that reconstruction time on FPGA is improved by 3× compared to previous FPGA implementation, whereas GPU implementation is 4× faster than the previously proposed GPU-based OMP architecture. The CPU implementation is 6× faster, compared with previous CPU-based implementation. The domain specific many-core acheives 24 times faster reconstruction time when compared to both GPU and CPU implementations.
Keywords :
compressed sensing; field programmable gate arrays; graphics processing units; greedy algorithms; image reconstruction; iterative methods; least squares approximations; multiprocessing systems; time-frequency analysis; CPU; CS signal reconstruction; GPU-based OMP architecture; OMP CS reconstruction; OMP algorithm; Virtex-7 FPGA; compressive sensing; convex relaxation; domain specific many-core; graphics processing units; greedy algorithm; iterative hard thresholding algorithm; least square error; local optimization algorithms; matching pursuit algorithms; nonconvex optimization algorithms; orthogonal matching pursuit; sparsity analysis; Computer architecture; Field programmable gate arrays; Graphics processing units; Hardware; Image reconstruction; Kernel; Matching pursuit algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
Type :
conf
DOI :
10.1109/ISCAS.2015.7168797
Filename :
7168797
Link To Document :
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