Development of chip scale package for DRAM

In order to assemble a chip scale package (CSP), a die with centralized bonding pads was mounted on a printed circuit board (PCB) using adhesive film, and was wire-bonded through a slot formed along the PCB center area, followed by encapsulation. After solder ball attachment, a PCB strip was divided into individual packages by punching. As the whole process is available with current equipment and materials, the assembly cost for this CSP is very low. The package height is lower than 1.0 mm, and the body size is larger than the die size only by 0.4 mm at each side. The ball pitch and size are 0.75 mm and 0.35 mm, respectively. The ball matrix was depopulated at the center area by two rows, leaving sufficient space for wire bonding. The package has passed reliability tests, including the level 3 preconditioning test, 240 hours of pressure cooker tests, and 1000 cycles of temperature cycling at board level as well as at component level. Through this work, it was has been verified that this CSP is one of the most cost-effective CSP solutions for DRAM devices