• DocumentCode
    3317739
  • Title

    Effects of stress concentration on metal voiding during dielectric deposition

  • Author

    Naeem, Munir D. ; Flaitz, Philip L. ; Chidambarrao, Dureseti

  • Author_Institution
    Microelectron. Div., IBM Corp., Hopewell Junction, NY, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    270
  • Lastpage
    275
  • Abstract
    The reliability of back end of line (BEOL) metallization for interconnection of semiconductor devices is extremely important. It is necessary that the metal lines be void free to meet electromigration requirements for advanced semiconductor devices. The reactive ion etching (RIE) of Al-Cu (0.5%) metallization is suspected to cause metal voids. Our systematic study of metal voids reveals the role of stress and stress concentration in void formation during dielectric material deposition after interconnect patterning by RIE. The stress simulation confirms the stress concentration at certain points on metal lines that lead to void formation. The role of side-wall (SW) angles of metal lines formed by RIE in stress concentration has been investigated. The effect of different dielectric materials such as spin on glass (SOG) and chemical vapor deposited (CVD) tetraethyl oxysilane (TEOS) on void formation has also been studied
  • Keywords
    aluminium alloys; copper alloys; dielectric thin films; electromigration; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; internal stresses; sputter etching; stress analysis; voids (solid); Al-Cu metallization; AlCu; AlCu-SiO2; CVD TEOS dielectrics; CVD tetraethyl oxysilane dielectrics; RIE; back end of line metallization; dielectric deposition; dielectric material deposition; dielectric materials; electromigration; interconnect patterning; interconnection; metal line side-wall angles; metal lines; metal voiding; metal voids; reactive ion etching; reliability; semiconductor devices; spin on glass dielectrics; stress concentration; stress concentration effects; stress simulation; void formation; Chemical vapor deposition; Dielectric materials; Electromigration; Etching; Glass; Lead; Metallization; Semiconductor device reliability; Semiconductor devices; Stress;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Manufacturing Technology Symposium, 1999. Twenty-Fourth IEEE/CPMT
  • Conference_Location
    Austin, TX
  • ISSN
    1089-8190
  • Print_ISBN
    0-7803-5502-4
  • Type

    conf

  • DOI
    10.1109/IEMT.1999.804832
  • Filename
    804832