Title :
Structure design for submicron MOSFET on ultra thin SOI
Author :
Yamaguchi, Y. ; Iwamatsu, T. ; Oda, H. ; Inoue, Y. ; Nishimura, T. ; Akasaka, Y.
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
Abstract :
In order to overcome the degradation of source-to-drain breakdown voltage (BV/sub dso/) in ultrathin SOI MOSFETs due to parasitic bipolar action, a gate overlapped LDD (lightly doped drain) structure was introduced for drain engineering. By the reduction of drain electric field and parasitic resistance at the source n/sup -/ region, the breakdown voltage was improved while keeping current drivability. The effect of channel doping level on BV/sub dso/ that affects the parasitic bipolar current gain was also investigated. Considering these two factors, guidelines for the structure design of submicron MOSFETs on ultrathin SOI are presented.<>
Keywords :
doping profiles; electric breakdown of solids; insulated gate field effect transistors; semiconductor-insulator boundaries; Si-SiO/sub 2/; channel doping level; current drivability; drain electric field; gate overlapped LDD; parasitic bipolar action; parasitic resistance; source-to-drain breakdown voltage; submicron MOSFET; ultra thin SOI; Degradation; Doping; Electric resistance; Guidelines; MOSFET circuits;
Conference_Titel :
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1990.237129
