A half-micron CMOS technology using ultra-thin silicon on insulator

Author

Woerlee, P.H. ; Juffermans, C. ; Lifka, H. ; Manders, W. ; Lansink, F.M.O. ; Paulzen, G.M. ; Sheridan, P. ; Walker, A.

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

583

Lastpage

586

Abstract

A 0.5 mu m CMOS technology on ultra-thin film SIMOX SOI (silicon on insulator) material is described. The technology, material quality, and device properties are discussed. The impact of TiSi/sub 2/ salicidation on the NMOS device breakdown, self-heating, and anomalous hot carrier degradation of NMOS devices is discussed in detail. Furthermore, the successful fabrication of a large circuit with 70000 transistors using a 0.5 mu m technology on ultra-thin SOI material is presented.<>

Keywords

CMOS integrated circuits; electric breakdown of solids; hot carriers; integrated circuit technology; semiconductor-insulator boundaries; 0.5 micron; CMOS technology; NMOS device breakdown; Si-SiO/sub 2/; TiSi/sub 2/ salicidation; device properties; hot carrier degradation; material quality; self-heating; ultra-thin film SIMOX SOI; CMOS technology; Circuits; Degradation; Electric breakdown; Fabrication; Hot carriers; MOS devices; Semiconductor films; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237131

Filename

237131