Design considerations for pipelined continuous-time incremental Sigma-Delta ADCs

This paper addresses design considerations for power-efficient pipelined continuous-time (CT) incremental Sigma-Delta (IΣΔ) ADC architectures. By pipelining identical CT IΣΔ ADC stages, the proposed architecture provides the design freedom coming from both the pipeline ADC and the IΣΔ ADC. In searching for a low-power solution given a target resolution, different configurations are examined analytically and simulated using behavioral models. For further power reduction, power-efficient circuits are proposed to implement the active blocks in each configuration. Based on the architecture-level analysis, a configuration that leads to minimum power-area consumption is chosen and implemented as a test-case using the proposed circuit blocks. Post-layout simulations show that the test-case ADC, with 3.2-kHz bandwidth, achieves a peak SNDR of 82.5-dB while dissipating a total power of 18.27-μW.