High density ceramic chip carrier: a 50 ohm impedance solution with a 2× increase in wiring density for flip chip applications

IBM Microelectronics Division has recently developed and shipped its first advanced wiring density chip carriers which provide 50 Ω impedance, via size down to 55 μm diameter and 34 μm line widths for high density I/O flip chip applications. The alumina chip carriers use thick film molybdenum features which can provide a wiring channel between 225 μm pitch chip I/O connections for voltage and signal wiring. In some applications, the number of signal wiring layers can be reduced by a factor of two. The high density voltage and ground layers provide a low inductance path which minimizes voltage drop across the carrier, thereby optimizing chip power distribution. This characteristic is particularly important for high frequency operation. In many high chip I/O applications, the increased wiring density permits the use of up to 4 die shrinks, which can reduce overall module costs significantly. The increased wiring density is compatible with CPGA, CCGA, CBGA and CLGA form factors. This paper summarizes the key electrical attributes of the package and compares results for two design variations with advanced wiring chip carrier fabrication. It is shown that both design variations result in a 50 Ω impedance package. Additionally, both designs result in improved power distribution with a reduction in signal switching noise. For a fully populated array design, 30% or more reduction in signal switching noise is obtained