Title :
A wide-margin, multiple-fan-in NOR gate for Josephson decoder
Author_Institution :
Hypres, Inc., Elmsford, NY, USA
Abstract :
The design and testing of a Josephson-junction NOR gate with a fan-in of six used for a single-stage 6-bit decoder are reported. This NOR gate design has the advantages of very wide operating margins (about +or-67%, theoretically), insensitivity to global processing and/or temperature variations, and the capability of many fan-ins without trading off speed and margins. A cross section (3 bits) of a 6-bit decoder has been built and tested with +or-33% bias margin. The single NOR gate has been tested up to 2 GHz clock rate.<>
Keywords :
NOR circuits; decoding; superconducting logic circuits; 2 GHz; 6 bit; Josephson decoder; Josephson-junction; NOR gate; bias margin; clock rate; design; fan-in; multiple-fan-in; single-stage 6-bit decoder; testing; wide operating margins; Clocks; Decoding; Temperature; Testing;
Conference_Titel :
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1990.237166
