Title :
A bipolar-EPROM (BI-EPROM) structure for 3.3 V operation and high speed application
Author :
Matsukawa, N. ; Masuda, K. ; Miyamoto, J.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A novel BI-EPROM structure, which has a vertical PNP bipolar transistor in the drain of the conventional EPROM cell, is proposed for future low-voltage and high-speed nonvolatile memories. In the read operation, the large cell current is obtained by the embedded bipolar function. Moreover, since its drain is made of an N-base, it has a high immunity against the soft-write phenomenon and can tolerate a higher channel current. It can be programmed by applying high voltages to both the source and the gate, while the drain is biased 0 V or negative voltage. Its feasibility is confirmed by a test vehicle with a 0.8 mu m technology.<>
Keywords :
BIMOS integrated circuits; EPROM; integrated circuit technology; 0.8 micron; 3.3 V; BI-EPROM structure; bipolar-EPROM; embedded bipolar function; feasibility; high speed memories; large cell current; low voltage memories; nonvolatile memories; operation; read operation; soft write immunity; vertical PNP bipolar transistor; Bipolar transistors; EPROM; Nonvolatile memory; Testing; Vehicles; Voltage;
Conference_Titel :
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1990.237167
