FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator

A system level design framework for FPGA-based DSP design is presented. The design flow utilizes System Generator, a system level tool developed by Xilinx, and links it to an "in-house" architectural synthesis tool, IRIS. Whilst System Generator allows FPGA-based Intellectual Property (IP) cores to be incorporated into the design flow, it does not address the timing and latency problems introduced by the cores which can be considerable, particularly when the cores are pipelined. These problems are addressed by the IRIS synthesis tool. The paper describes the tools, their interaction and illustrates the flow using an 8-tap Transpose-Form Retimed Delayed LMS (TF-RDLMS) adaptive filter.