Critical-path optimization for efficient hardware realization of lifting and flipping DWTs

The pair of scaling constants of lifting scheme for DWT computation are perfect inverse of each other while those of flipping scheme are not perfect inverse of each other. However, flipping-scheme is preferred over the lifting-scheme for area-delay efficient hardware implementation of 2-D DWT due to its smaller critical-path. In this paper we present critical-path analysis of lifting and flipping schemes and propose a low-complexity data-path for lifting based DWT. We have shown that the critical-path delay (CPD) of lifting DWT is higher by only 2 full-adder (FA) delay than that of flipping DWT. Moreover, due to the saving of multipliers, lifting scheme offers a better area delay efficient structure than the flipping scheme for parallel realization of 2-D DWT. In this paper, we propose efficient realization of both lifting and flipping DWT. Compared with the best of the available flipping-based 2-D DWT structure, the proposed lifting-based and flipping-based structures for block-size 16 involve 74% less and 73% less area-delay-product (ADP), and offer nearly 6.38 and 6.72 times higher throughput, respectively. Compared with similar lifting based existing design, the proposed lifting-based structure involves 15.38% less ADP for the same block-size.