An FPGA-based processor for shogi mating problems

After the success of DEEP BLUE in computer chess, shogi, or Japanese chess is a next challenging target in artificial intelligence for game playing. The complexity and huge search space of shogi have been motivating researchers to make shogi programs, but none of them is competent enough to play against human experts. To improve the competence of shogi programs, it is a promising approach to develop dedicated hardware systems. However inflexible architecture and lack of hardware resource have been the significant problems in hardware development. The flexibility and recent progress in the gate size of FPGAs are expected to give solutions to the problems. As a first step to shogi hardware, we implemented modules to generate check and defense moves in tsume-shogi, or mating problems in shogi. With the latest FPGA, we successfully implemented all modules on a single chip and eliminated the bottleneck of memory bandwidth. In this paper we describe a procedure for parallel move generation in tsume-shogi hardware and architecture of the modules implemented on an FPGA. A discussion about the performance of the hardware is also included in the paper. The hardware is roughly estimated to work 10-50 times faster than software.