Characterization of speed and stability of BiNMOS gates with a bipolar and PMOSFET merged structure

Author

Momose, H. ; Maeda, T. ; Inoue, K. ; Kamohara, I. ; Kobayashi, T. ; Urakawa, Y. ; Maeguchi, K.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

231

Lastpage

234

Abstract

A base and drain merged bipolar-PMOSFET (BiPMOS) structure was examined. A latch-up phenomenon in this structure associated with a parasitic PNP bipolar was investigated and verified experimentally and analytically. From the standpoint of stability in circuit operation a latch-up-free structure was considered. To evaluate the contribution of this technology to circuit speed performance, the structure was applied to a BiNMOS gate. It was found that the delay time if a merged BiNMOS gate was improved by 10-20% compared with that of the conventional BiNMOS gate. Moreover, at a fan-out of 1, this gate achieved a higher speed than the CMOS gate.<>

Keywords

BIMOS integrated circuits; integrated logic circuits; logic gates; characterization; circuit speed performance; delay time; latch-up phenomenon; latch-up-free structure; merged BiNMOS gate; merged BiPMOS gate; merged bipolar-PMOSFET structure; parasitic PNP bipolar; stability; Circuit stability; Delay effects;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237186

Filename

237186