Modeling and simulation of the 16 megabit EPROM cell for write/read operation with a compact SPICE model

Author

Gigon, F.

Author_Institution

SGS-Thomson Microelectron., Grenoble, France

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

205

Lastpage

208

Abstract

A compact SPICE model to stimulate an EPROM cell is presented. Starting from the physics-based MOS model and taking into account impact ionization and the parasitic bipolar effect, ´avalanche´ leading to snap-back is described. Gate current, based on the ´lucky-electron´ model, is integrated in one dimension along the channel. The floating gate voltage is induced by external biases and trapped charges. Threshold voltage as seen from the control gate is considered. Results from simulations of transient behavior during writing and reading operations are shown; they were satisfactorily used for the submicron cell in the design of the 16 megabit EPROM.<>

Keywords

EPROM; circuit analysis computing; digital simulation; equivalent circuits; integrated memory circuits; semiconductor device models; transient response; 16 Mbit; EPROM cell; compact SPICE model; external biases; floating gate voltage; gate current; impact ionization; lucky electron model; parasitic bipolar effect; physics-based MOS model; simulation; snap-back; submicron cell; threshold voltage; transient behavior; trapped charges; write/read operation; EPROM; Impact ionization; SPICE; Threshold voltage; Voltage control; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237192

Filename

237192