Gate-aided drain to field breakdown of high voltage NMOS devices

A limitation on-high-voltage CMOS application is gate-aided breakdown of n/sup +/ drain to field (BVdf ). The three-dimensional effect of the n/sup +/ junction bird´s beak shape, the presence of an oxide spacer, and lateral diffusion of the field implant must be analyzed to optimize BVdf. Extensive simulations are used to show that n/sup +/ junction position under the bird´s beak gradient dominates both breakdown voltage and gate dependency. Nonoverlap of junction edge to polysilicon gate by spacer technology is shown to improve BVdf. It is demonstrated that bird´s beak angle and drain implant energy variations add little to improve BVdf, while increasing field implant doses act to reduce it.<>