Design issues for achieving latchup-free, deep trench-isolated, bulk, non-epitaxial, submicron CMOS

Author

Bhattacharya, S. ; Banerjee, S. ; Lee, J. ; Tasch, A. ; Chatterjee, A.

Author_Institution

Microelectron. Res. Center, Texas Univ., Austin, TX, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

185

Lastpage

188

Abstract

The authors describe the improvement of latchup immunity through the use of deep trench-isolation in bulk nonepitaxial CMOS technology. An extensive two-dimensional numerical analysis of a deep trench-isolated, bulk CMOS structure was performed using PISCES-IIB. It is shown that deep trench-isolation, in conjunction with properly designed layout, trench geometry, and doping profiles, can increase the holding voltage significantly. This improvement is due to an increase of the two-dimensional spreading resistance of the conductivity-modulated well and substrate regions in the latched-up state that is caused by the deep trench. By increasing the holding voltage to above the power supply voltage (3.3 V in deep submicron CMOS), latchup-free CMOS can be achieved even in bulk, nonepitaxial substrates.<>

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; semiconductor device models; 3.3 V; PISCES-IIB; ULSI; bulk nonepitaxial CMOS technology; conductivity-modulated well; deep trench-isolation; doping profiles; latchup immunity; latchup-free CMOS; layout; nonepitaxial substrates; submicron CMOS; trench geometry; two-dimensional numerical analysis; two-dimensional spreading resistance; CMOS technology; Doping profiles; Geometry; Numerical analysis; Power supplies; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237197

Filename

237197