Bipolar circuit reliability simulation

Author

Burnett, D. ; Horiuchi, T. ; Ku, Chen-Wei

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

181

Lastpage

184

Abstract

A model for bipolar hot-carrier degradation has been implemented into the BERT circuit reliability simulator, thus allowing both bipolar and BiCMOS circuit degradation to be simulated. The bipolar module consists of a preprocessor and post-processor for SPICE that require no modification to the SPICE code. Experimental results indicate that the degradation due to alternating reverse-forward stressing representative of BiCMOS gate operation agrees with the Delta I/sub B/ model from DC measurements. The base current degradation for a single device due to electrostatic discharge stress and the offset voltage degradation for an emitter-coupled pair due to DC stress are accurately predicted by the simulator.<>

Keywords

BIMOS integrated circuits; bipolar integrated circuits; circuit analysis computing; circuit reliability; digital simulation; electrostatic discharge; hot carriers; semiconductor device models; BERT; BiCMOS circuit degradation; DC stress; ESD; SPICE; base current degradation; bipolar hot-carrier degradation; bipolar module; circuit reliability simulation; electrostatic discharge stress; emitter-coupled pair; gate operation; model; offset voltage degradation; postprocessor; preprocessor; reverse-forward stressing; BiCMOS integrated circuits; Bit error rate; Circuit simulation; Degradation; Electrostatic discharge; Electrostatic measurements; Hot carriers; SPICE; Stress measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237198

Filename

237198