A co-simulation study of adaptive EPIC computing

Author

Gheorghita, Valentin Stefan ; Wong, Weng-Fai ; Mitra, Tulika ; Talla, Surendranath

Author_Institution

Politehnica Univ. of Bucharest, Romania

fYear

2002

fDate

16-18 Dec. 2002

Firstpage

268

Lastpage

275

Abstract

Reconfigurable computing offers the embedded systems designers the flexibility of application specific optimizations on a generic platform. In this paper, we are concerned with a fine-grain, tightly coupled, dynamically reconfigurable architecture we call Adaptive EPIC. A generic EPIC architecture is augmented with a dynamically reconfigurable structure. In this paper, we describe an experimental setup to evaluate the performance of such a processor. Our results show that such architecture can offer significant performance improvements for low frequency, and hence low power, core processors.

Keywords

application specific integrated circuits; embedded systems; low-power electronics; reconfigurable architectures; virtual machines; adaptive EPIC computing; application specific optimizations; co-simulation study; dynamically reconfigurable architecture; embedded systems; fine-grain architecture; generic platform; low frequency core processors; low power core processors; reconfigurable computing; tightly coupled architecture; Computational modeling; Computer architecture; Design optimization; Field programmable gate arrays; Hardware; Logic arrays; Logic devices; Programmable logic arrays; Programmable logic devices; Reconfigurable logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on

Print_ISBN

0-7803-7574-2

Type

conf

DOI

10.1109/FPT.2002.1188691

Filename

1188691