Efficient single-chip implementation of SHA-384 and SHA-512

Author

McLoone, M. ; McCanny, J.V.

Author_Institution

Sch. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK

fYear

2002

fDate

16-18 Dec. 2002

Firstpage

311

Lastpage

314

Abstract

The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms is described in this paper. The compact implementation achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs). This is believed to be the first SHA-384/SHA-512 hardware implementation to be reported in the literature.

Keywords

Internet; cryptography; message authentication; table lookup; 479 Mbit/s; Internet; SHA-384; SHA-512; authentication; look-up tables; security; shift register design approach; single-chip implementation; Algorithm design and analysis; Authentication; Cryptography; Data security; Hardware; NIST; National security; Protection; Transport protocols; Wireless application protocol;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on

Print_ISBN

0-7803-7574-2

Type

conf

DOI

10.1109/FPT.2002.1188699

Filename

1188699