A 2.3 mu m/sup 2/ memory cell structure for 16 Mb NAND EEPROMs

Author

Shirota, R. ; Nakayama, R. ; Kirisawa, R. ; Momodomi, M. ; Sakui, K. ; Itoh, Y. ; Aritome, S. ; Endoh, T. ; Hatori, F. ; Masuoka, F.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

103

Lastpage

106

Abstract

A NAND structure memory cell with 2.2*1.05 mu m/sup 2/ size per bit, based on a 0.6 mu m design rule, has been developed for 16 Mb flash EEPROMs. The cell size is about 64% of the smallest 16 Mb EPROM cell so far reported. An extremely small cell can be realized by the following technologies: (1) newly developed 0.3 mu m space self-aligned stacked gate patterning, (2) a NAND structured cell array which contains 16 memory transistors in series, and (3) high-voltage field isolation technology used to isolate neighboring bits. The first and second technologies reduce the length of the cell by 67.6% compared with the conventional NAND structured cell using the same design rule, while the third technology reduces the width by 84.6%.<>

Keywords

EPROM; NAND circuits; VLSI; integrated circuit technology; integrated memory circuits; 0.6 micron; 16 Mbit; NAND structure memory cell; cell size; design rule; flash EEPROMs; high-voltage field isolation technology; self-aligned stacked gate patterning; EPROM; Isolation technology; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237216

Filename

237216