Title :
Testing for resistive open defects in FPGAs
Author :
Tahoori, Mehdi Baradaran
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
This paper presents a new technique for detecting resistive open defects in FPGAs. This technique is based on the reconfigurability feature of FPGAs. Using this technique, the delay of a defective path is increased several times more than the delay of the fault-free path, resulting in a higher resolution in detectability of resistive open defects in FPGAs, even at lower tester speed. Various detailed SPICE simulations are performed to validate this method. Also, a test configuration generation scheme is presented for the entire FPGA.
Keywords :
circuit simulation; field programmable gate arrays; integrated circuit testing; logic simulation; logic testing; FPGA reconfigurability features; FPGA testing; defective path delay; detectability resolution; fault-free path delay; resistive open defects; test configuration generation scheme; tester speed; Analytical models; Automatic testing; Capacitance; Circuit faults; Circuit testing; Delay estimation; Field programmable gate arrays; Logic testing; Timing; Voltage;
Conference_Titel :
Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on
Print_ISBN :
0-7803-7574-2
DOI :
10.1109/FPT.2002.1188704
