Lateral distribution of interface states in PMOSFETs

Author

Dimauro, J.L. ; Henning, A.K.

Author_Institution

Thayer Sch. of Eng., Dartmouth Coll., Hanover, NH, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

81

Lastpage

84

Abstract

Precise measurements of the lateral distribution of interface states in PMOSFETs, before and after drain-avalanche-hot-carrier (DAHC) stress, are reported. The results are analyzed in the context of simultaneous gate current and substrate current measurements, and 2-D numerical simulations. Comparison of the results to similar NMOSFET measurements demonstrates that electron injection across the Si-SiO/sub 2/ interface during DAHC stress creates amphoteric interface states along the drain-region interface and negative trapped oxide charge along the channel-region interface.<>

Keywords

hot carriers; insulated gate field effect transistors; interface electron states; semiconductor-insulator boundaries; silicon; silicon compounds; DAHC stress; PMOSFETs; Si-SiO/sub 2/; amphoteric interface states; channel-region interface; drain-avalanche-hot-carrier; drain-region interface; interface states; lateral distribution; negative trapped oxide charge; simultaneous gate current; substrate current measurements; Charge measurement; Current measurement; Drain avalanche hot carrier injection; Electron traps; Interface states; MOSFET circuits; Numerical simulation; Stress measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237221

Filename

237221