An Efficient Design of a Reversible Barrel Shifter

The key objective of today´s circuit design is to increase the performance without the proportional increase in power consumption. In this regard, reversible logic has become an immensely promising technology in the field of low power computing and designing. On the other hand, data shifting and rotating are required in many operations such as arithmetic and logical operations, address decoding and indexing etc. In this consequence, barrel shifters, which can shift and rotate multiple bits in a single cycle, have become a common design choice for high speed applications. For this reason, this paper presents an efficient design of a reversible barrel shifter. It has also been shown that the new circuit outperforms the previously proposed one in terms of number of gates, number of garbage outputs, delay and quantum cost.