Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs

Symmetric FIR filters, which provide linear phases, are frequently used in digital signal processing. This paper presents the design and implementation of a novel architecture for symmetric FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of processing signal boundaries, which occurs in finite length signal processing (e.g. image processing). Based on bit parallel arithmetic, our architecture is fully scalable and parameterised. It takes into account the details of the symmetry and exploits the features of Xilinx Virtex FPGAs. The implementation leads to considerable area savings compared to conventional implementations (based on a hard router), at the expense of using a clock doubler, which reduces the overall processing speed. The latter is however still high enough to achieve real time performance. Moreover, our architecture can match the speed of a conventional implementation if the filter output is going to be decimated, as it is the case in multirate applications (e.g. wavelets).