DocumentCode
3319065
Title
FPGA implementation of MFNN for image registration
Author
Gharpure, D.C. ; Puranik, M.S.
Author_Institution
Dept. of Instrum. Sci., Univ. of Pune, India
fYear
2002
fDate
16-18 Dec. 2002
Firstpage
364
Lastpage
367
Abstract
The multilayer feedforward neural network (MFNN) is modified to simplify hardware realization and at the same time retain the accuracy of detection. The results obtained have been found to be comparable to the software simulation algorithm which is used as a test base. The MFNN implementation involves low hardware complexity, good noise immunity and fast circuitry.
Keywords
feedforward neural nets; field programmable gate arrays; image registration; neural chips; FPGA implementation; fast circuitry; hardware realization; image registration; low hardware complexity; multilayer feedforward neural network; noise immunity; Circuit simulation; Circuit testing; Feedforward neural networks; Field programmable gate arrays; Image registration; Multi-layer neural network; Neural network hardware; Neural networks; Software algorithms; Software testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on
Print_ISBN
0-7803-7574-2
Type
conf
DOI
10.1109/FPT.2002.1188712
Filename
1188712
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