DocumentCode
3319093
Title
The hardware implementation of a genetic algorithm model with FPGA
Author
Lei, Tu ; Ming-Cheng, Zhu ; Jing-Xia, Wang
Author_Institution
EDA Technol. Center, Shenzhen Univ., China
fYear
2002
fDate
16-18 Dec. 2002
Firstpage
374
Lastpage
377
Abstract
A genetic algorithm (GA) is a robust parallel calculation method based on natural selection, which can be applied to the distributed and concentrated industry optimizing control process. The hardware function of a GA operation can be implemented by an FPGA. In this paper, a hardware implementation method of a GA based on an FPGA is presented. The results of this research can be applied to the study and implementation of evolvable hardware (EHW).
Keywords
field programmable gate arrays; genetic algorithms; FPGA; evolvable hardware; genetic algorithm model; hardware implementation; Biological cells; Electronic design automation and methodology; Field programmable gate arrays; Genetic algorithms; Genetic mutations; Hardware; Logic circuits; Random number generation; Signal generators; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on
Print_ISBN
0-7803-7574-2
Type
conf
DOI
10.1109/FPT.2002.1188714
Filename
1188714
Link To Document