Title :
Profile leverage in self-aligned epitaxial Si or SiGe base bipolar technology
Author :
Comfort, J.H. ; Patton, G.L. ; Cressler, J.D. ; Lee, W. ; Crabbe, E.F. ; Meyerson, B.S. ; Sun, J.Y.-C. ; Stork, J.M.C. ; Lu, P.-F. ; Burghartz, J.N. ; Warnock, J. ; Scilla, G. ; Toh, K.-Y. ; D´Agostino, M. ; Stanis, C. ; Jenkins, K.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
The authors have developed a planar, self-aligned, epitaxial Si or SiGe-base bipolar technology and explored intrinsic profile design leverage for high-performance devices in three distinct areas: transit time reduction, collector-base (CB) junction engineering, and emitter-base (EB) junction engineering. High f/sub T/ Si (30-50 GHz) and SiGe (50-70 GHz) epi-base devices were integrated with trench isolation and polysilicon load resistors to evaluate ECL (emitter coupled logic) circuit performance. A 15% enhancement in ECL circuit performance was observed for SiGe relative to Si devices with similar base doping profiles in a given device layout. Minimum SiGe-base ECL gate delays of 24.6 ps (8 mW) were obtained. Lightly doped spacers were positioned in both the EB and CB junctions to tailor junction characteristics (leakage, tunneling, and avalanche breakdown), reduce junction capacitances, and thereby obtain an overall performance improvement.<>
Keywords :
Ge-Si alloys; bipolar integrated circuits; bipolar transistors; doping profiles; elemental semiconductors; emitter-coupled logic; integrated circuit technology; semiconductor materials; silicon; 24.6 ps; 30 to 70 GHz; ECL; Si; SiGe; avalanche breakdown; base doping profiles; bipolar technology; collector-base junction engineering; emitter-base junction engineering; gate delays; intrinsic profile design leverage; junction capacitances; leakage; performance improvement; polysilicon load resistors; transit time reduction; trench isolation; tunneling; Circuit optimization; Coupling circuits; Design engineering; Doping profiles; Germanium silicon alloys; Isolation technology; Logic circuits; Logic devices; Resistors; Silicon germanium;
Conference_Titel :
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1990.237235
