Power-Aware Test Framework for Network-on-Chip

In this paper, we propose the power-aware test framework for network-on-chip (NoC). First, the possibility of using embedded processor and on-chip network are introduced and evaluated with benchmark system to test the other embedded cores. Second, a new generation method of test pattern, which is called ´don´t care mapping´, is presented to reduce the power consumption of on-chip network. The experimental results show that the power consumption is reduced up to 8% at the communication components.