Disruptive design solutions for frequency generation in silicon RFIC

This paper presents some new approaches for frequency generation in silicon RF integrated circuits, from either the circuit or the architecture point of view. While a phase locked loop (PLL) is classically brought into play whenever a frequency synthesis is needed, the design of key building blocks such as the RF frequency divider is a very challenge. Concerning the latter, the synchronized ring oscillator (SRO), which provides dual-modulus division at frequency above 20 GHz while consuming little power, is presented. Alternative solutions to the classical PLL, such as injection locked oscillator (ILO) and factorial delay locked loop (F-DLL) are presented as well. Advantages and drawbacks of these approaches are discussed, based upon simulation and experimental measurements.