DocumentCode :
3319278
Title :
Electrical Modeling of Lithographic Imperfections
Author :
Chan, Tuck-Boon ; Ghaida, Rani S. ; Gupta, Puneet
Author_Institution :
EE Dept, Univ. of California, Los Angeles, CA, USA
fYear :
2010
fDate :
3-7 Jan. 2010
Firstpage :
423
Lastpage :
428
Abstract :
Lithographic wavelength of 193 nm has been used for past few generations of patterning and is likely to remain in use for next few technology generations (at least till 28 nm technology half-node) as well. This deep sub-wavelength patterning has resulted in wafer shapes not resembling drawn rectilinear shapes. The resulting non-rectangular devices and wires are not handled by current generation modeling and analyses methods. In this paper, we present a survey of electrical modeling methods for such lithographic imperfections especially on transistor layers. We also discuss use contexts of such models as well as briefly present electrical implications of the likely future patterning candidate, namely double patterning.
Keywords :
nanolithography; semiconductor process modelling; ultraviolet lithography; current generation modeling; deep sub-wavelength patterning; double patterning; electrical modeling; lithographic imperfections; nonrectangular devices; nonrectangular wires; transistor layers; wafer shapes; wavelength 193 nm; Analytical models; Circuit simulation; Context modeling; Lighting; Lithography; Performance analysis; Semiconductor device manufacture; Semiconductor device modeling; Shape; Solid modeling; lithographic imperfections; mosfet; non-rectangular; transistor;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2010. VLSID '10. 23rd International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
978-1-4244-5541-6
Type :
conf
DOI :
10.1109/VLSI.Design.2010.24
Filename :
5401209
Link To Document :
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