Design of Phase Locked-Loop for Very Slow Sine-Wave Signals

The paper describes the design procedure of phase-locked loop (PLL). This PLL is used in measurement chain with pressure sensor and band-pass sigma-delta modulator to synchronize the input slow sine-wave signal from sensor with driving clock (signal from PLL) of modulator. The frequency of input sine-wave signal is 15,625 kHz. The PLL output (voltage controlled-oscillator) has to generate 62,5 kHz square driving signal. The paper shows design process of most important stages in CMOS 0.7 mum AMIS technology and it also presents simulation results, which confirm the design process of these blocks.